The drive of the semiconductor industry to improve integrated chip performance through scaling has led to the exponential growth of active devices on a chip. The combination of increased device density and shrinking dimensions has led to an increase in the RC (resistance times capacitance) signal delay in the back end of line (BEOL) interconnect wiring. In the past, this problem was addressed by the industry using a three-prong approach. First using alternative chip design, more levels of wiring were added at the smallest wiring dimensions to decrease the signal transit distances. Second, to reduce interconnect resistivity, aluminum was replaced with copper, a metal with ˜30% lower resistivity. Finally, capacitance was reduced by replacing the interconnect insulator with a lower dielectric constant material (low k) including the introduction of porosity.
However, the continued drive to improve chip performance through device scaling has led to additional challenges in the BEOL, specifically the increased resistivity stemming from grain boundary scattering in the Cu wiring and damage to the porous low k material caused by patterning and integration. To mitigate both problems an alternate integration approach, subtractive copper etch (sub-etch Cu) was developed to replace the typical damascene integration flow.
FIG. 1 is a flowchart that illustrates a typical subtractive copper etching process. The technique of FIG. 1 starts from a blanket Cu film deposition, thus minimizing electron scattering, and creates Cu lines with large crystals (>1 μm). FIGS. 2A-2D are conceptual diagrams illustrating successive lateral cross-sectional views of an article processed by the technique of FIG. 1.
Step 110 includes forming at least one polish stop 240 on a surface of an integrated circuit substrate 220. The at least one polish stop 240 may assist in attaining a level plane in a subsequent polishing step, for example, chemical mechanical polishing. In some processes, the polish stop 240 may include a material that is harder than the material removed during polishing, for example, metal that may be deposited on the substrate 220 and then polished. Step 130 includes depositing the metal 260 over one or both of the surface of the integrated circuit substrate 220 and the at least one polish stop 240. The metal 260 may include grain boundaries 262. Step 150 includes annealing the deposited metal 260. Step 170 includes polishing the deposited metal 260. Step 190 includes patterning the metal 260 to form metal interconnects 264.